Device packaging advances are making it nearly impossible to access device leads on PC boards. For example, new advances have allowed for high primary input/output (I/O) pin count on an application specific integrated circuit (ASIC), but allow for no observability of the connections between the ASIC and board it is used on. Level sensitive scan design, for example, boundary scan, has emerged as a way to solve the increasing difficulty in testing packaged devices. Boundary scan methodology is based on a formally adopted IEEE/ANSI standard, IEEE/ANSI 1149.1-1990. This design-in test technique provides virtual access to devices and allows for simplified pattern generation to detect and diagnose structural board faults.
Most design test techniques utilize some form of serial scan test path. At the ASIC level, design test of device logic 14 on the ASIC 10, as shown in FIG. 1, may be accomplished with the use of level sensitive scan design style flip-flops (not shown). The flip-flops are connected together to form one serial scan chain and there may be several serial scan chains or test paths on an ASIC. When all the flip-flops in the ASIC are scannable, testing of the device logic of the ASIC is simplified. A vector pattern or input test data is scanned into the serial scan chain(s). One system clock is applied and the resulting output test data is scanned out of the serial scan chain(s). Scan testing results in very high fault coverage. This is especially important on large ASICs. Scan testing further allows the use of other third party test pattern generation tools to create test vectors.
At the system level, for example, at a board level including several ASICs as shown in FIG. 1, scanning in and out test data is used to test the device logic 15 of the ASICs 10 and the interconnects therebetween. The number of test pins needed to access the board is minimized. The term `boundary scan` has come to describe the serial scan path that is associated with testing of the input/output latches on an ASIC 10, FIG. 1, and, therefore, its interconnects as well. Boundary scan provides test access to device pins 12 by associating a serial shift registry element, or scan cell 14, with each signal pin 12. The boundary scan cells 14 are linked together to form a shift register chain around the device boundary. These scan cells 14 can then be used to control and observe the device pins 12. Each ASIC 10 on the board may have its test data out pin (TDO) connected to the test data in pin (TDI) of the next ASIC in the chain. This creates a daisy chain serial connection of all the ASICs 10 on the board and, therefore, when scanning in a test pattern, all of an ASIC's test data is scanned in at one time.
The boundary scan standard, IEEE/ANSI 1149.1-1990 is a collection of design rules applied principally at the integrated circuit (IC) level. This standard makes it possible to employ software to control the growing cost of designing and producing digital systems. The primary benefit of this standard is its ability to transform extremely difficult printed circuit board testing problems into well-structured problems that software can solve easily and swiftly. Adhering to this standard enables the purchase of both third party hardware testers and software that will automatically generate test patterns to test the ICs.
Boundary scan is similar to the scan methodology described above using level sensitive scan design type flip-flops. The difference is that, as the name infers, the scan circuitry is associated with flip-flops that make up the ASIC's boundary, i.e., primary in and out flip-flops. All of the boundary flip-flops on each ASIC are connected together into a serial scan test path. The test patterns are shifted into each ASIC under control of test access port (TAP) controller 16 clocked by a test clock input (TCK). After the test patterns are shifted into the serial scan test paths, one test clock cycle is applied and the resulting output data is shifted out of the serial scan path under control of the test access port controller. Upon checking the response data, faults can be detected. The TAP controller provides the necessary clock, data, and control function needed to use the serial scan paths for testing.
The boundary scan standard, IEEE/ANSI 1149.1-1990, mentioned above, includes design rules for the input cells and the output cells used for boundary scan testing. The specific design of the input cell for boundary scan testing includes a pair of multiplexers in the input path. The specific design of the output cell for boundary scan testing includes a pair of multiplexers in the output path. The placement of the multiplexers with respect to the I/O cells of the data path is variable and, as a result, introduces a variable amount of delay into the input path to chip, such as an ASIC, or into the output path of a chip, such as an ASIC. As a result, the amount of time necessary for a signal to pass into a chip and the amount of time for a signal to pass out of a chip also vary and must be considered in designing a printed circuit board.
Printed circuit boards are typically designed for use in a computer system or control system. A clock is included in most if not all digital computing systems or control systems. The function of the clock is to pace the operation of a digital system. A clock, such as a system clock, will be provided to a chip or board. All operations are dictated by the clock pulses. In other words, certain operations and the resulting signals produced typically have to be done in a certain number of clock cycles. Ideally, operations will have to be completed in one clock cycle. This provides for the quickest operating computer systems or control systems. Operations not only must be complete, but the resulting signal or data usually must move from one physical place to another physical place within a clock cycle. It takes a certain amount of time for signals or data to pass through conductors such as those found within a chip or such as foil found on a printed circuit. This time can be calculated quite precisely. The timing delays onto and off of a chip are generally fixed. Once these are determined, the placement of the various components on the printed circuit board is the only real time variable left that a designer can play with. Typically the length of the conductor on the printed circuit board must be short enough to allow signals to pass between the chips in a clock cycle or number of clock cylces. It should be noted that there are few chips that allow a number of clock cylces for data or other signals to pass.
Another view of this is that the path between the chips must be short enough so that the time for the signal to pass over the path added to the time associated with the delay of the output of one chip, and the time associated with the delay of the input of the next chip must be less than the clock period specified. The time necessary for the signal to travel between two chips can be varied by varying the physical location of the chips. If there is little time remaining in the clock cycle after considering delays, the length of the path of gold foil between the chips must be short to assure that the signal will be at its destination before the next clock cycle. The placement of the chips determines the path length between the chips. Board layout must assure that signals will be able to be at their destinations within a clock cycle or period. This is why the designer must consider board layout carefully.
It is very well known how much time it takes for a signal to pass along a specific length of gold foil on a printed circuit board or along any length of a particular conductor. For example, if the delay of the signal off of one chip and the delay of a signal onto another chip are both short, the length of the path of gold foil between the chips can be long. From the printed circuit board designers standpoint, these two chips could be placed most any distance apart. On the other hand, when the delay of the signal off of one chip and the delay of a signal onto another chip are both long, the length of the path of gold foil on the printed circuit board between the chips must be short. Therefore, the physical placement of two chips is critical since they must be close. Placement of the components on a printed circuit board can be extremely difficult or nearly impossible if the delays onto and off of particular chips and all relatively long.
This design consideration interferes with implementations of other design concepts. One such design concept is generally termed floor planning. The concept of floor planning is that the various components can be placed anywhere on the printed circuit board. In other words, a designer merely has to fit the various components on a board and does not have to consider the length of foil or conductor between the components. The concept of floor planning is much more difficult to implement when delay times have to be considered in the design or layout of the printed circuit board. Typically there is one critical path that must be considered. This may effect several other chips.
The design consideration also interferes with substituting components which may have different delay times for the signal passing onto the chip or off of the chip. A new revision may require a different component. In addition, suppliers of the components may produce revised components in which the timing has been varied. Accommodating such revisions would be easier if timing delays onto the chip and off of the chip were known or fixed, rather than variable.
For these reasons and others, there is a need in the art for enhancements to minimize or substantially shorten signal delay times on and off a chip. There is also a need to accomplish this such that the standard logic tests and testing devices used in present boundary scan schemes can be used in an enhanced version. Preferably, the fabrication testing of the test logic of a level sensitive scan design. There is also a need to accomplish this task with a minimal amount of cost to chip manufacturers so that they will not be adverse to implementing such a boundary testing scheme. There is also a need for a minimal amount of change in logic in the input cells and the output cells.